1. Field of the Invention
The present invention relates to a method for forming excellent conformity due to improved surface sensitivity
2. Description of the Prior Art
Recently, demand for dynamic random access memory (DRAM) has rapidly increased owing to widespread use of electronic equipment. In particular, it is applied relatively widely in the information industry in the computer hardware. In addition to being applied in the information industry, large-scale integration (LSI), very large scale integration (VLSI), and ultra large-scale integration (ULSI) must use greatly dynamic random access memory. In next century, the fabricated technology of the dynamic random access memory (DRAM) is still performed a primary role. Due to electronic, information, and communication product intent to light, thin, short, and quick, which high density and large capacity of the dynamic random access memory with demand is increased.
A memory device with higher cell density naturally has a higher memory capacity, and accordingly has a lower fabrication cost. In order to increase the memory capacity in a DRAM device, a strategy to increase a memory cell density is generally taken. A higher device density is usually achieved by reducing structures dimension of an integrated circuit (IC), such as line width, line pitch distance, transistor gate, or coupled capacitor.
A DRAM cell typically includes a field-effect transistor (FET) and a capacitor coupled to the FET. A DRAM device usually includes a large number of DRAM cells arranged in an array structure. Each DRAM cell can store one binary data through a capacitor charge status. A charged capacitor stores a binary data of "1", and a discharged capacitor stores a binary data of "0". Its coupled FET through a voltage status applied on its drain region does the action of charging or discharging. A desired FET can also be selected by a bit line and word line. The word line is typically coupled to each gate of the FETs in the DRAM array, and the bit line is typically coupled to each drain of the FETs of the DRAM array. The bit line provides the voltage status to the FET. The word line is used to turn on/off the FET. Through a selected pair of the bit line and the word line, a desired FET is selected and is written-in a binary data to the coupled capacitor. The stored binary data can also be read out by selecting the FET and switching the bit line to a compactor circuit to obtain the charge status of the coupled capacitor. The stored binary data in the selected DRAM cell is therefore obtained.
The capacitor stores charges on its lower and upper electrode surfaces, which are separated by a dielectric layer. The lower electrode is coupled to the source of the FET. The amount of stored charges in one capacitor depends on its capacitance. The capacitance is proportional to its electrode surface, such as the lower electrode surface, inversely proportional to the distance between the upper electrode and the lower electrode, and proportional to the dielectric constant.
In order to reduce the device dimension, the surface of the lower electrode is usually also reduced. In this manner, it capacitance is reduced. If the capacitance of the capacitor is reduced, a lot of issues may be induced. For example, a decay mechanism and a charge leakage may cause an error content of the stored binary data due to a small quantity of stored charges, which therefore has small tolerance of charge variance. Generally, in order to prevent the error content of the stored binary data, the capacitor is necessarily refreshed in a certain period of time, which is also called a refreshing cycle time. If the capacitance is smaller, the refreshing cycle time is shorter, and the refreshing process is necessarily more often performed. During each time of the refreshing process, the DRAM can not fulfills its function. This is called a dead time. A smaller capacitance has more dead time, and the efficiency of the DRAM performance is reduced. Moreover, a smaller capacitance needs a more sensitive amplifier, which results in a more complicated circuit and greater fabrication cost.
It was found that nitride this down to the very scale would result in an unexpected high resistance in capacitor node. This high resistance was attributed to poly grain oxidation in storage neck area. This phenomenon is more severe as node critical dimension decreases. It was also found that the issue of surface sensitivity is more serious for thinner nitride deposition, highly possible to enable oxidation path through poly/oxide interface. Some evidence also supports this hypothesis such as alleviating surface sensitivity during nitride deposition and adding additional thin nitride layer between storage node (SN) and IPD.